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etrontech em6a9320bib etron technology, inc. no. 6, technology rd. v, hsinchu science park, hsinchu, taiwan 30078, r.o.c. tel: (886)-3-5782345 fax: (886)-3-5778671 etron technology, inc. reserves the right to change products or specific ation without notice. 4m x 32 bit ddr synchronous dram (sdram) etron confidential advanced (rev 1.0, july /2012) features ? fast clock rate: 200/250 mhz ? differential clock ck & ck input ? 4 bi-directional dqs. data transactions on both edges of dqs (1dqs / byte) ? dll aligns dq and dqs transitions ? edge aligned data & dqs output ? center aligned data & dqs input ? 4 internal banks, 1m x 32-bit for each bank ? programmable mode and extended mode registers - cas latency: 2, 2.5, 3 - burst length: 2, 4, 8 - burst type: sequential & interleave ? all inputs except dq?s & dm are at the positive edge of the system clock ? 4 individual dm control for write masking only ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? industrial operating temperature: -40~8
? power supplies: v dd & v ddq = 2.5v 0.2v ? interface: sstl_2 i/o compatible ? 144-ball 12 x 12 x 1.4mm lfbga package -pb and halogen free overview the em6a9320 ddr sdram is a high-speed cmos double data rate synchronous dram containing 128 mbits. it is internally configured as a quad 1m x 32 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, ck). data out puts occur at both rising edges of ck and ck . read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of a bankactivate command, which is then followed by a read or write command. the em6a9320 provides programmable read or write burst lengths of 2, 4, 8. an auto precharge function may be enabled to provide a self-timed row precharge that is initiat ed at the end of the burst sequence.the refresh functions , either auto or self refresh are easy to use. in addition, em6a9320 features programmable dll option. by having a pr ogrammable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications. table1. ordering information part number clock frequency data rate power supply package EM6A9320BIB-4IH 250mhz 500mbps/pin v dd 2.5v, v ddq 2.5v lfbga em6a9320bib-5ih 200mhz 400mbps/pin v dd 2.5v, v ddq 2.5v lfbga bi: indicates lfbga package b: indicates generation code i: indicates industrial grade h: indicates pb and halogen free for lfbga package
etrontech em6a9320bib etron confidential 2 rev 1.0 july /2012 figure 1. pin assignment (lfbga 144ball top view) a b c d e 123 f g h j dqs0 dm0 dq4 vddq dq6 dq5 dq7 vddq dq17 dq16 dq19 dq18 dqs2 dm2 dq21 dq20 dq22 dq23 vssq nc vssq vdd vddq vddq nc vddq vddq 7 dq31 vddq vdd vss vss vss vss vss vss 8 dq29 dq30 vssq vssq vss vss vss vss vss 9 dq28 vddq vssq vss vssq vssq vssq vssq vssq dq3 vddq vssq vss vssq vssq vssq vssq vssq dq2 dq1 vssq vssq vss vss vss vss vss dq0 vddq vdd vss vss vss vss vss vss 456 10 vssq nc vssq vdd vddq vddq nc vddq vddq 11 dm3 vddq dq26 vddq dq15 dq13 dm1 dq11 dq9 12 dqs3 dq27 dq25 dq24 dq14 dq12 dqs1 dq10 dq8 l ras nc nc a9 a5 nc ba1 a2 a11 ck ck nc k cas we vdd vdd nc vss vss a10 vdd vdd nc nc m cs nc ba0 a4 a6 a7 a0 a1 a3 a8 cke vref table 2. pin assignment by name (lfbga 144ball) symbol location symbol location symbol location symbol location symbol location symbol location symbol location symbol location a0 m4 dq6 c1 dq24 d12 ck l10 vddq b6 vss e5 vss j7 vssq g4 a1 m5 dq7 d1 dq25 c12 ck l11 vddq b7 vss e6 vss j8 vssq g9 a2 l5 dq8 j12 dq26 c11 cke m11 vddq b9 vss e7 vss k4 vssq h4 a3 m6 dq9 j11 dq27 b12 cs m1 vddq b11 vss e8 vss k9 vssq h9 a4 m7 dq10 h12 dq28 a9 ras l1 vddq d2 vss f5 vssq a3 vssq j4 a5 l8 dq11 h11 dq29 a8 cas k1 vddq d11 vss f6 vssq a10 vssq j9 a6 m8 dq12 f12 dq30 b8 we k2 vddq e3 vss f7 vssq c3 nc b3 a7 m9 dq13 f11 dq31 a7 vref m12 vddq e10 vss f8 vssq c4 nc b10 a8/ap m10 dq14 e12 dqs0 a1 vdd c6 vddq f3 vss g5 vssq c5 nc g3 a9 l7 dq15 e11 dqs1 g12 vdd c7 vddq f10 vss g6 vssq c8 nc g10 a10 k5 dq16 e2 dqs2 g1 vdd d3 vddq h3 vss g7 vssq c9 nc k8 a11 l6 dq17 e1 dqs3 a12 vdd d10 vddq h10 vss g8 vssq c10 nc k11 dq0 a6 dq18 f2 dm0 a2 vdd k3 vddq j3 vss h5 vssq d5 nc k12 dq1 b5 dq19 f1 dm1 g11 vdd k6 vddq j10 vss h6 vssq d8 nc l2 dq2 a5 dq20 h2 dm2 g2 vdd k7 vss d4 vss h7 vssq e4 nc l3 dq3 a4 dq21 h1 dm3 a11 vdd k10 vss d6 vss h8 vssq e9 nc l9 dq4 b1 dq22 j1 ba0 m3 vddq b2 vss d7 vss j5 vssq f4 nc l12 dq5 c2 dq23 j2 ba1 l4 vddq b4 vss d9 vss j6 vssq f9 nc m2
etrontech em6a9320bib etron confidential 3 rev 1.0 july /2012 figure 2. block diagram dll clock buffer command decoder column counter control signal generator address buffer refresh counter 4096 x 256 x 32 cell array (bank #0) row decoder row decoder 4096 x 256 x 32 cell array (bank #2) row decoder 4096 x 256 x 32 cell array (bank #3) row decoder column decoder column decoder column decoder column decoder mode register a8/ap a9 a10 a11 ba0 ba1 ~ a0 data strobe buffer dqs0~3 dq buffer dq31 dq0 ~ dm0~3 4096 x 256 x 32 cell array (bank #1) ck cke cs ras cas we ck
etrontech em6a9320bib etron confidential 4 rev 1.0 july /2012 pin descriptions table 3. pin details of em6a9320 symbol type description ck, ck input differential clock: ck, ck are driven by the system clock. all sdram input commands are sampled on the positive edge of ck. both ck and ck increment the internal burst counter and c ontrols the output registers. cke input clock enable: cke activates (high) and deactivates (low) the ck signal. if cke goes low synchronously with clock, the in ternal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. ba0, ba1 input bank activate: ba0 and ba1 define to which bank t he bankactivate, read, write, or bankprecharge command is being applied. they also define which mode register or extended mode register is loaded during a mode register set command. a0-a11 input address inputs: a0-a11 are sampled during the bank a ctivate command (row address a0-a11) and read/write command (column address a0- a 7 with a8 defining auto precharge) to select one location out of the 1m available in the respective bank. during a precharge command, a8 is sampled to determine if all banks are to be precharged (a8 = high). the address inputs also provide the op-code during a mode register set or extended mode register set command. cs input chip select: cs enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs is sampled high. cs provides for external bank selection on syst ems with multiple banks. it is considered part of the command code. ras input row address strobe: the ras signal defines the operation commands in conjunction with the cas and /we signals and is latched at the positive edges of ck. when ras and cs are asserted "low" and cas is asserted "high" either the bankactivate command or the precharge command is selected by the we signal. when the we is asserted "high," the bankactivate command is selected and the bank designated by ba is turned on to the active state. when the we is asserted "low," the precharge command is selected and the bank designated by ba is switched to the idle state after the precharge operation. cas input column address strobe: the cas signal defines the operation commands in conjunction with the ras and /we signals and is latched at the positive edges of ck. when /ras is held "high" and cs is asserted "low" the column access is started by asserting cas "low" then, the read or write command is selected by asserting we "high " or ?low". we input write enable: the we signal defines the operation commands in conjunction with the ras and cas signals and is latched at the positive edges of ck. the we input is used to select the bankactivate or precharge command and read or write command. dqs0-dqs3 input / output bidirectional data strobe: the dqsx signals are mapped to the following data bytes: dqs0 to dq0-dq7, dqs1 to dq8-dq15, dqs2 to dq16-dq23, and dqs3 to dq24-dq31. dm0 - dm3 input data input mask: dm0-dm3 are byte specific. i nput data is masked when dm is sampled high during a write cycle. dm3 masks dq31-dq24, dm2 masks dq23- dq16, dm1 masks dq15-dq8, and dm0 masks dq7-dq0. dq0 - dq31 input / output data i/o: the dq0-dq31 input and output data ar e synchronized with positive and negative edges of dqs0~dqs3. the i/os are byte-maskable during writes. v dd supply power supply: power for the input buffers and core logic. v ss supply ground: ground for the input buffers and core logic .
etrontech em6a9320bib etron confidential 5 rev 1.0 july /2012 v ddq supply dq power: provide isolated power to dqs for improved noise immunity. v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. v ref supply reference voltage for inputs: +0.5 x v ddq nc - no connect: no internal connection, these pins suggest to be left unconnected.
etrontech em6a9320bib etron confidential 6 rev 1.0 july /2012 operation mode table 4 shows the truth table for the operation commands. table 4. truth table (note (1), (2)) command state cken-1 cken dm ba1 ba0 a8 a11-a9, a7-0 cs ras cas we bankactivate idle (3) h x x v v row address l l h h bankprecharge any h x x v v l x l l h l precharge all any h x x x x h x l l h l write active (3) h x v v v l l h l l write and autoprecharge active (3) h x v v v h l h l l read active (3) h x x v v l l h l h read and autoprecharge active (3) h x x v v h column address a0~a7 l h l h mode register set idle h x x l l l l l l extended mode register set idle h x x l h op code l l l l no-operation any h x x x x x x l h h h device deselect any h x x x x x x h x x x burst stop active (4) h x x x x x x l h h l autorefresh idle h h x x x x x l l l h selfrefresh entry idle h l x x x x x l l l h h x x x selfrefresh exit idle (self refresh) l h x x x x x l h h h h x x x power down mode entry idle/active (5) h l x x x x x l h h h h x x x power down mode exit any (power down) l h x x x x x l h h h data mask enable (6) active h x h x x x x x x x x data mask disable active h x l x x x x x x x x note: 1. v = valid data, x = don't care, l = low level, h = high level 2. cke n signal is input level when commands are provided. cke n-1 signal is input level one clock cycl e before the commands are provided. 3. these are states of bank designated by ba0, ba1signals. 4. read burst stop with bst command for all burst types. 5. power down mode can not enter in the burst operation. when this command is asserted in the bur st cycle, device state is clock suspend mode. 6. dm0 ? dm3 can be enabled respectively.
etrontech em6a9320bib etron confidential 7 rev 1.0 july /2012 mode register set (mrs) the mode register stores the data for controlling various operating modes of a ddr sdram. it programs cas latency, burst type, and burst length to make the ddr sdram useful for a variety of applications. the default value of the mode register is not defined; therefore the mode regi ster must be written by the user. values stored in the register will be retained until the regi ster is reprogrammed. the m ode register is written by asserting low on cs , ras , cas , we , ba1 and ba0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and cke should be high). the state of address pins a0~a11 and ba0, ba1 in the same cycle in which cs , ras , cas and we are asserted low is written into the mode register. a minimum of two clock cycles, tmrd, are required to complete the write operation in the mode register. the mode register is divided into various fields depending on functionality. the burst length uses a0~a2, burst type uses a3, and cas lat ency (read latency from column addre ss) uses a4~a6. a logic 0 should be programmed to all the undefined addresses to ensure fu ture compatibility. rese rved states should not be used to avoid unknown device operation or incompatibility with future versions. refer to the table for specific codes for various burst lengths, burst types and cas latencies. table 5. mode register bitmap ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 0 t.m. cas latency bt burst length mode register a8 a7 test mode a6 a5 a4 cas latency a3 burst type a2 a1 a0 burst length 0 0 normal mode 0 0 0 reserved 0 sequential 000 reserved 1 0 dll reset 0 0 1 reserved 1 interleave 001 2 x 1 test mode 0 1 0 2 010 4 0 1 1 3 011 8 1 0 0 reserved 100 reserved ba0 mode 1 0 1 reserved 101 reserved 0 mrs 1 1 0 2.5 110 reserved 1 emrs 1 1 1 reserved 111 reserved ? burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst length to be 2, 4, and 8. table 6. burst length a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
etrontech em6a9320bib etron confidential 8 rev 1.0 july /2012 ? addressing mode select field (a3) the addressing mode can be one of two modes, either interleave mode or sequential mode. both sequential mode and interleave mode support burst length of 2, 4, and 8. table 7. addressing mode a3 addressing mode 0 sequential 1 interleave ? burst definition, addressing sequence of sequential and interleave mode table 8. burst address ordering start address burst length a2 a1 a0 sequential interleave x x 0 0, 1 0, 1 2 x x 1 1, 0 1, 0 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 4 x 1 1 3, 0, 1, 2 3, 2, 1, 0 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 8 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 ? cas latency field (a6~a4) this field specifies the number of cl ock cycles from the assertion of t he read command to the first read data. the minimum whole value of cas latency depends on the frequency of ck. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) cas latency x t ck table 9. cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 reserved 1 0 1 reserved 1 1 0 2.5 clocks 1 1 1 reserved
etrontech em6a9320bib etron confidential 9 rev 1.0 july /2012 ? test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to "00" in normal operation. table 10. test mode a8 a7 test mode 0 0 normal mode 1 0 dll reset x 1 test mode ? (ba0, ba1) table 11. mrs/emrs ba1 ba0 a11 ~ a0 rfu 0 mrs cycle rfu 1 extended functions (emrs) extended mode register set (emrs) the extended mode register set stores the data for enab ling or disabling dll and selecting output driver strength. the default value of the ext ended mode register is not defined, ther efore must be written after power up for proper operation. the extended mode regi ster is written by asserting low on cs , ras , cas , and we . (the device should have all banks idle with no bursts in progr ess prior to writing into the mode register, and cke should be high)the state of a0 ~ a11 and ba1 are wr itten in the mode register in the same cycle as ck , ras , cas , and we going low. the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. a1 is used for setting driver strengt h. two clock cycles are required to complete the write operation in the ex tended mode register. the mode register contents can be changed using the same command and clock cycle requirement s during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on ba0 is used for emrs. refer to the table for specific codes. table 12. extended mode register bitmap ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 rfu must be set to ?0? ds dll extended mode register ba0 mode a1 drive strength a0 dll 0 mrs 0 full 0 enable 1 emrs 1 reserved 1 disable
etrontech em6a9320bib etron confidential 10 rev 1.0 july /2012 table 13. absolute maximum rating rating symbol item -4i/5i unit note v in , v out input, output voltage - 0.5 ~ v ddq +0.5 v 1,2 v dd , v ddq power supply voltage -1 ~ 3.6 v 1,2 t a ambient temperature -40~85 c 1 t stg storage temperature - 55~150 c 1 t solder soldering temperature (10s) 260 c 1 p d power dissipation 2.0 w 1 i os short circuit output current 50 ma 1 note1: stress greater than those listed under ?absolut e maximum ratings? may cause permanent damage of the devices note2: these voltages are relative to vss table 14. recommended d.c. operating conditions (sstl_2 in/out, t a = -40 ~ 85 c) symbol parameter min. max. unit note v dd power supply voltage 2.3 2.7 v 1 v ddq power supply voltage(for i/o ) 2.3 2.7 v 1 v ref input reference voltage 0.49 x v ddq 0.51 x v ddq v v tt termination voltage v ref ? 0.04 v ref + 0.04 v v ih(dc) input high voltage v ref + 0.15 v ddq + 0.3 v v il(dc) input low voltage v ssq - 0.3 v ref - 0.15 v i il input leakage current - 2 2 a i oz output leakage current - 5 5 a i oh output high current -16.2 - ma v oh = 1.95v i ol output low current 16.2 - ma v ol = 0.35v table 15. capacitance (v dd = 2.5v, f = 1mhz, t a = 25 c) symbol parameter min. max. unit c in1 input capacitance (ck, ck ) 1.5 2.5 pf c in2 input capacitance (all other input-only pins) 1.5 2.5 pf c i/o dm, dq, dqs input/output capacitance 3.5 4.5 pf note: these parameters are guaranteed by design, periodically sampled and are not 100% tested. table 16. decoupling capacitance guide line symbol parameter value unit c dc1 decouping capacitance between v dd and v ss 0.1+0.01 f c dc2 decouping capacitance between v ddq and v ssq 0.1+0.01 f
etrontech em6a9320bib etron confidential 11 rev 1.0 july /2012 table 17. d.c. characteristics (v dd =2.5v 0.2v, t a =-40~85 c) -4i -5i parameter & test condition symbol max. unit operating current: one bank; active-precharge; t rc =t rc (min); t ck =t ck (min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. idd0 220 210 ma operating current : one bank; active-read-precharge; bl=4; t rc =t rc (min); t ck =t ck (min); lout=0ma; address and control inputs changing once per clock cycle idd1 260 240 ma precharge power-down standby current: all banks idle; power-down mode; t ck =t ck (min); cke=low idd2p 75 75 ma idle standby current : cke = high; cs =high(deselect); all banks idle; t ck =t ck (min); address and control inputs changing once per clock cycle; v in =v ref for dq, dqs and dm idd2n 100 100 ma active power-down standby current : one bank active; power- down mode; cke=low; t ck =t ck (min) idd3p 75 75 ma active standby current : cs =high;cke=high; one bank active ; t rc =t rc (max);t ck =t ck (min);address and control inputs changing once per clock cycle; dq,dqs,and dm input s changing twice per clock cycle idd3n 230 220 ma operating current burst read : bl=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); lout=0ma;50% of data changing on every transfer idd4r 440 420 ma operating current burst write : bl=2; writes; continuous burst ;one bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); dq,dqs,and dm changing twice per clock cycle; 50% of data changing on every transfer idd4w 440 420 ma auto refresh current : t rc =t rfc (min); t ck =t ck (min) idd5 330 300 ma self refresh current: self refresh mode ; cke 0.2v;t ck =t ck (min) idd6 6 6 ma burst operating current 4 bank operation: four bank interleaving reads; bl=4;with auto precharge; t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active, read , or write command idd7 600 570 ma note: 1. stress greater than those listed under "abs olute maximum ratings" may cause permanent damage of the device. 2. all voltages are referenced to v ss . 3. these parameters depend on the cycle rate and t hese values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 4. power-up sequence is described in later page.
etrontech em6a9320bib etron confidential 12 rev 1.0 july /2012 table 18. electrical characteristics and reco mmended a.c. operating conditions (v dd = 2.5v 0.2v, t a = -40~85 c) -4i -5i symbol parameter min. max. min. max. unit cl = 2 - - 7.5 12 ns cl = 2.5 - - 6 12 ns t ck clock cycle time cl = 3 4 10 5 7.5 ns t ch clock high level width 0.45 0.55 0.45 0.55 t ck t cl clock low level width 0.45 0.55 0.45 0.55 t ck t dqsck dqs-out access time from ck, ck -0.6 0.6 -0.6 0.6 ns t ac output access time from ck, ck -0.7 0.7 -0.7 0.7 ns t dqsq dqs-dq skew - 0.4 - 0.4 ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck t rpst read postamble 0.4 0.6 0.4 0.6 t ck t dqss ck to valid dqs-in 0.72 1.25 0.72 1.25 t ck t wpres dqs-in setup time 0 - 0 - ns t wpre dqs write preamble 0.25 - 0.25 - t ck t wpst dqs write postamble 0.4 0.6 0.4 0.6 t ck t dqsh dqs in high level pulse width 0.4 - 0.4 - t ck t dqsl dqs in low level pulse width 0.4 - 0.4 - t ck t is address and control input setup time 0.7 - 0.7 - ns t ih address and control input hold time 0.7 - 0.7 - ns t ds dq & dm setup time to dqs 0.4 - 0.4 - ns t dh dq & dm hold time to dqs 0.4 - 0.4 - ns t hp clock half period t clmin or t chmin - t clmin or t chmin - ns t qh dq/dqs output hold time from dqs t hp - t qhs - t hp - t qhs - ns t rc row cycle time 55 - 55 - ns t rfc refresh row cycle time 60 - 70 - ns t ras row active time 40 100k 40 100k ns t rcd active to read or write delay 15 - 15 - ns t rp row precharge time 15 - 15 - ns t rrd row active to row active delay 3 - 2 - t ck t wr write recovery time 3 - 3 - t ck t mrd mode register set cycle time 2 - 2 - t ck t dal auto precharge write recovery + precharge time t wr + t rp - t wr + t rp - t ck t xsrd self refresh exit to read command delay 200 - 200 - t ck t pdex power down exit time t ck + t is - t ck + t is - ns t refi average refresh interval time - 15.6 - 15.6 s t ipw control and address input pulse width 2.2 - 2.2 - ns t dipw dq & dm input pulse width (for each input) 1.75 - 1.75 - ns t hz data-out high-impedance window from ck/ ck - 0.7 - 0.7 ns t lz data-out low-impedance window from ck/ ck -0.7 0.7 -0.7 0.7 ns t qhs data hold skew factor - 0.45 - 0.5 ns dvw output data valid window t qh - t dqsq - t qh - t dqsq - ns t xsnr exit self-refresh to non-read command 75 - 75 - ns t ccd cas# to cas# delay time 1 - 1 - t ck
etrontech em6a9320bib etron confidential 13 rev 1.0 july /2012 table 19. recommended a.c. operating conditions (t a = -40~85 c, v dd =2.5v 0.2v) -4i/5i parameter symbol min. max. unit input high voltage (ac) v ih (ac) v ref + 0.31 - v input low voltage (ac) v il (ac) - v ref ? 0.31 v input different voltage, ck and ck inputs v id (ac) 0.7 v ddq + 0.6 v input crossing point voltage, ck and ck inputs v ix (ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v note: 1. all voltages are referenced to v ss . 2. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 3. power-up sequence is described in note 5. 4. a.c. test conditions table 20. sstl_2 interface reference level of output signals (v ref ) 0.5 * v ddq output load reference to the test load input signal levels v ref +0.31 v / v ref -0.31 v input signals slew rate 1 v/ns reference level of input signals 0.5 * v ddq figure 3. sstl_2 a.c. test load dq, dqs z0=50 ? 50 ? 30pf 0.5 * vddq
etrontech em6a9320bib etron confidential 14 rev 1.0 july /2012 5. power up sequence power up must be performed in the following sequence. 1) apply power to v dd before or at the same time as v ddq, v tt and v ref when all input signals are held "nop" state and maintain cke ?low?. 2) start clock and maintain stable condition for minimum 200us. 3) issue a ?nop? command and keep cke ?high? 4) issue a ?precharge all? command. 5) issue emrs ? enable dll. 6) issue mrs ? reset dll. (an additional 200 clock cycles are required to lock the dll). 7) precharge all banks of the device. 8) issue two or more auto refresh commands. 9) issue mrs ? with a8 to low to initialize the mode register.
etrontech em6a9320bib etron confidential 15 rev 1.0 july /2012 timing waveforms figure 4. activating a specifi c row in a specific bank ck ck cke cs ras cas we ra address ba ba0,1 don?t care high ra=row address ba=bank address
etrontech em6a9320bib etron confidential 16 rev 1.0 july /2012 figure 5. trcd and trrd definition ck ck address act nop command nop act nop nop rd/wr nop row row col bank a bank b bank b t rrd t rcd don?t care ba0,ba1 figure 6. read command ck ck cke cs ras cas we ca a0 ~ a7 a8 don?t care high en ap dis ap ba ba0,1 ca=column address ba=bank address en ap=enable autoprecharge dis ap=disable autoprecharge
etrontech em6a9320bib etron confidential 17 rev 1.0 july /2012 figure 7. read burst required cas latencies (cl=2) ck ck command read nop nop nop nop nop bank a, col n address dqs dq cl=2 don?t care do n=data out from column n burst length=4 3 subsequent elements of data ou t appear in the programmed order following do n do n read burst required cas latencies (cl=2.5) ck ck command read nop nop nop nop nop bank a, col n address dqs dq cl=2.5 don?t care do n=data out from column n burst length=4 3 subsequent elements of da ta out appear in the progr ammed order following do n do n
etrontech em6a9320bib etron confidential 18 rev 1.0 july /2012 read burst required cas latencies (cl=3) do n ck ck command read nop nop nop nop nop bank a, col n address dqs dq cl=3 don?t care do n=data out from column n burst length=4 3 subsequent elements of data out appear in the programmed order following do n
etrontech em6a9320bib etron confidential 19 rev 1.0 july /2012 figure 8. consecutive read bursts required cas latencies (cl=2) ck ck command read nop read nop nop nop bank, col n address dqs dq cl=2 do n don?t care bank, col o do o do n (or o)=data out from column n (or column o) burst length=4 or 8 (if 4, the bursts are concaten ated; if 8, the second burst interrupts the first) 3 subsequent elements of data out appear in the programmed order following do n 3 (or 7) subsequent elements of data out appear in the programmed order following do o read commands shown must be to the same device
etrontech em6a9320bib etron confidential 20 rev 1.0 july /2012 consecutive read bursts required cas latencies (cl=2.5) do o ck ck command read nop read nop nop nop bank, col n address dqs dq cl=2.5 don?t care bank, col o do n (or o)=data out from column n (or column o) burst length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of data out appear in the programmed order following do n 3 (or 7) subsequent elements of data out appear in the programmed order following do o read commands shown must be to the same device do n
etrontech em6a9320bib etron confidential 21 rev 1.0 july /2012 consecutive read bursts required cas latencies (cl=3) do o ck ck command read nop read nop nop nop bank, col n address dqs dq cl=3 don?t care bank, col o do n (or o)=data out from column n (or column o) burst length=4 or 8 (if 4, the bursts are concaten ated; if 8, the second burst interrupts the first) 3 subsequent elements of data out appear in the programmed order following do n 3 (or 7) subsequent elements of data out appear in the programmed order following do o read commands shown must be to the same device do n
etrontech em6a9320bib etron confidential 22 rev 1.0 july /2012 figure 9. non-consecutive read bursts required cas latencies (cl=2) ck ck command read nop nop read nop nop bank, col n address dqs dq cl=2 don?t care bank, col o do n (or o)=data out from column n (or column o) burst length=4 3 subsequent elements of da ta out appear in the progr ammed order following do n (and following do o) do o do n non-consecutive read bursts required cas latencies (cl=2.5) ck ck command read nop nop read nop nop bank, col n address dqs dq cl=2.5 don?t care bank, col o nop do n (or o)=data out from column n (or column o) burst length=4 3 subsequent elements of data out appear in the programmed order following do n (and following do o) do n do o
etrontech em6a9320bib etron confidential 23 rev 1.0 july /2012 non-consecutive read bursts required cas latencies (cl=3) ck ck command read nop nop read nop nop bank, col n address dqs dq cl=3 don?t care bank, col o nop do n (or o)=data out from column n (or column o) burst length=4 3 subsequent elements of data out appear in the programmed order following do n (and following do o) do o do n
etrontech em6a9320bib etron confidential 24 rev 1.0 july /2012 figure 10. random read accesses required cas latencies (cl=2) do p do n' do o do o' do p' do q ck ck command read read read read nop nop bank, col n address dqs dq cl=2 don?t care bank, col o bank, col p bank, col q do n, etc. =data out from column n, etc. n', etc. =the next data ou t following do n, et c. according to the programmed burst order burst length=2,4 or 8 in ca ses shown. if burs t of 4 or 8, the burst is interrupted reads are to active rows in any banks do n random read accesses required cas latencies (cl=2.5) do p do n' do o do o' do p' ck ck command read read read read nop nop bank, col n address dqs dq cl=2.5 don?t care bank, col o bank, col p bank, col q do n, etc. =data out from column n, etc. n' , e t c . = t h e n e x t d a t a out following do n, etc. accordin g to the programmed burst order burst length=2,4 or 8 in cases shown. if burst of 4 or 8, the burst is interrupted reads are to active rows in any banks do n
etrontech em6a9320bib etron confidential 25 rev 1.0 july /2012 random read accesses required cas latencies (cl=3) do p do n' do o do o' ck ck command read read read read nop nop bank, col n address dqs dq cl=3 don?t care bank, col o bank, col p bank, col q do n, etc. =data out from column n, etc. n', etc. =the next data out following do n, etc. accord ing to the programmed burst order burst length=2,4 or 8 in cases shown. if burst of 4 or 8, the burst is interrupted reads are to active rows in any banks do n
etrontech em6a9320bib etron confidential 26 rev 1.0 july /2012 figure 11. terminating a read burst required cas latencies (cl=2) ck ck command read nop bst nop nop nop bank a, col n address dqs dq cl=2 don?t care do n = data out from column n cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of data out appear in the programmed order following do n do n terminating a read burst required cas latencies (cl=2.5) ck ck command read nop bst nop nop nop bank a, col n address dqs dq cl=2.5 don?t care do n = data out from column n cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of data out appear in the programmed order following do n do n
etrontech em6a9320bib etron confidential 27 rev 1.0 july /2012 terminating a read burst required cas latencies (cl=3) ck ck command read nop bst nop nop nop bank a, col n address dqs dq cl=3 don?t care do n = data out from column n cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of data out appear in the programmed or der following do n do n
etrontech em6a9320bib etron confidential 28 rev 1.0 july /2012 figure 12. read to write required cas latencies (cl=2) read bst nop write nop nop bank, col n cl=2 don?t care bank, col o di o tdqss min do n (or o)= data out from column n (or column o) burst length= 4 in the cases shown (applies for burst s of 8 as well; if burst length is 2, the bst command shown can be nop) 1 subsequent element of data out appear s in the programmed order following do n data in elements are ap plied following di o in the programmed order do n ck ck command address dqs dq dm
etrontech em6a9320bib etron confidential 29 rev 1.0 july /2012 read to write required cas latencies (cl=2.5) ck ck command read bst nop nop write nop bank, col n address dqs dq cl=2.5 don?t care min tdqss di o dm bank, col o do n (or o)= data out from column n (or column o) burst length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the bst command shown can be nop) 1 subsequent element of data out appears in the programmed order following do n data in elements are applied following di o in the programmed order do n
etrontech em6a9320bib etron confidential 30 rev 1.0 july /2012 read to write required cas latencies (cl=3) ck ck command read bst nop nop write nop bank, col n address dqs dq cl=3 don?t care bank, col o min tdqss di o dm do n (or o)= data out from column n (or column o) burst length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the bst command shown can be nop) 1 subsequent element of data out appears in the programmed order following do n data in elements are applied following di o in the programmed order do n
etrontech em6a9320bib etron confidential 31 rev 1.0 july /2012 figure 13. read to precharge required cas latencies (cl=2) ck ck command read nop pre nop nop act bank a, col n address dqs dq cl=2 don?t care bank (a or all) bank a, row t rp do n = data out from column n cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of data out appear in the programmed order following do n precharge may be applied at (bl/2) tck after the read command note that precharge may not be issued before tras ns after the active command for applicable banks the active command may be applied if trc has been met do n
etrontech em6a9320bib etron confidential 32 rev 1.0 july /2012 read to precharge required cas latencies (cl=2.5) ck ck command read nop pre nop nop act bank a, col n address dqs dq cl=2.5 don?t care bank (a or all) bank a, row t rp do n = data out from column n cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of data ou t appear in the programmed order following do n precharge may be applied at (bl/ 2) tck after the read command note that precharge may not be issu ed before tras ns after the active command for applicable banks the active command may be a pplied if trc has been met do n
etrontech em6a9320bib etron confidential 33 rev 1.0 july /2012 read to precharge required cas latencies (cl=3) ck ck command read nop pre nop nop act bank a, col n address dqs dq cl=3 don?t care bank (a or all) bank a, row t rp do n = data out from column n cases shown are either unin terrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of data ou t appear in the programmed order following do n precharge may be applied at ( bl/2) tck after the read command note that precharge may not be issu ed before tras ns after the active command for applicable banks the active command may be ap plied if trc has been met do n
etrontech em6a9320bib etron confidential 34 rev 1.0 july /2012 figure 14. write command ck ck cke cs ras cas we ca a0 ~ a7 a8 don?t care high en ap dis ap ba ba0,1 ca=column address ba=bank address en ap=enable autoprecharge dis ap=disable autoprecharge
etrontech em6a9320bib etron confidential 35 rev 1.0 july /2012 figure 15. write max dqss ck ck command write nop nop nop bank a, col n address dqs dq tdqss don?t care dm t0 t1 t2 t3 t4 t5 t6 t7 max di n di n = data in for column n 3 subsequent elements of data in are applied in the programmed order following di n a non-interrupted burst of 4 is shown a8 is low with the wri te command (auto precharge disabled)
etrontech em6a9320bib etron confidential 36 rev 1.0 july /2012 figure 16. write min dqss ck ck command write nop nop nop bank a, col n address dqs dq tdqss dm t0 t1 t2 t3 t4 t5 t6 min di n don?t care di n = data in for column n 3 subsequent elements of data in are applied in the programmed order following di n a non-interrupted bu rst of 4 is shown a8 is low with the wri te command (auto precharge disabled)
etrontech em6a9320bib etron confidential 37 rev 1.0 july /2012 figure 17. write burst nom, min, and max tdqss ck ck command write nop nop nop bank , col n address dqs dq tdqss (nom) don?t care dm t0 t1 t2 t3 t4 t5 t6 t7 di n t8 t9 t10 t11 nop nop dqs dq tdqss (min) dm di n dqs dq tdqss (max) dm di n di n = data in for column n 3 subsequent elements of da ta are applied in the programmed order following di n a non-interrupted bu rst of 4 is shown a8 is low with the write command (auto precharge disabled) dm=dm0 ~ dm3
etrontech em6a9320bib etron confidential 38 rev 1.0 july /2012 figure 18. write to write max tdqss ck ck command write nop write nop bank , col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 nop nop dqs dq tdqss (max) dm di n bank , col o di o don?t care di n , etc. = data in for column n,etc. 3 subsequent elements of data in are appl ied in the programmed order following di n non-interrupted bursts of 4 are shown dm= dm0 ~ dm3 3 subsequent elements of data in are appl ied in the programmed order following di o
etrontech em6a9320bib etron confidential 39 rev 1.0 july /2012 figure 19. write to write max tdqss, non consecutive ck ck command write nop nop write bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 nop nop dqs dq tdqss (max) dm di n bank col o di o don?t care di n, etc. = data in for column n, etc. 3 subsequent elements of data in are applied in the programmed order following di n non-interrupted bursts of 4 are shown dm= dm0 ~ dm3 3 subsequent elements of data in are applied in the programmed order following di o
etrontech em6a9320bib etron confidential 40 rev 1.0 july /2012 figure 20. random write cycles max tdqss
etrontech em6a9320bib etron confidential 41 rev 1.0 july /2012 figure 21. write to read max tdqss non interrupting ck ck command write nop nop read bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n bank col o t10 t11 nop twtr cl=3 don?t care di n, etc. = data in for column n, etc. 1 subsequent elements of data in are applied in the programmed order following di n twtr is referenced from the first positive ck edge after the last data in pair dm= dm0 ~ dm3 a non-interrupted burst of 2 is shown a8 is low with the write comman d (auto precharge is disabled) the read and write commands are to the same de vices but not necessarily to the same bank t12 nop
etrontech em6a9320bib etron confidential 42 rev 1.0 july /2012 figure 22. write to read max tdqss interrupting ck ck command write nop nop read bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n bank col o t10 t11 nop twtr cl=3 don?t care di n, etc. = data in for column n, etc. 1 subsequent elements of data in are a pplied in the programmed order following di n twtr is referenced from the first positive ck edge a fter the last data in pair dm= dm0 ~ dm3 an interrupted burst of 8 is show n, 2 data elements are written a8 is low with the write command (auto precharge is disabled) the read and write commands are to the same devices but not necessari ly to the same bank t12
etrontech em6a9320bib etron confidential 43 rev 1.0 july /2012 figure 23. write to read max tdqss, odd number of data, interrupting ck ck write nop nop read bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n bank col o t10 t11 nop twtr cl=3 don?t care di n = data in for column n twtr is referenced from the first posi tive ck edge after the last data in pair (not the last desired data in element) dm= dm0 ~ dm3 an interrupted burst of 8 is show n, 1 data elements are written a8 is low with the write comman d (auto precharge is disabled) the read and write commands are to the same devices but not necessarily to the same bank t12 command
etrontech em6a9320bib etron confidential 44 rev 1.0 july /2012 figure 24. write to precharge max tdqss, non- interrupting ck ck command write nop nop nop bank a, col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 pre dqs dq tdqss (max) dm di n bank (a or al) t10 t11 nop twr trp don?t care di n = data in for column n 1 subsequent elements of data in are ap plied in the programmed order following di n twr is referenced from the first positive ck edge after the last data in pair dm= dm0 ~ dm3 a non-interrupt ed burst of 2 is shown a8 is low with the write comman d (auto precharge is disabled)
etrontech em6a9320bib etron confidential 45 rev 1.0 july /2012 figure 25. write to precharge max tdqss, interrupting ck ck command write nop nop pre bank a, col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n t10 t11 nop twr trp *1 *2 don?t care di n = data in for column n twr is referenced from the first positive ck edge after the last data in pair dm= dm0 ~ dm3 an interrupted burst of 4 or 8 is shown, 2 data el ements are written a8 is low with the write comman d (auto precharge is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed bu rst length of 4, dqs becomes don't care at this point *1 *1 *1 bank (a or all)
etrontech em6a9320bib etron confidential 46 rev 1.0 july /2012 figure 26. write to precharge max tdq ss odd number of data interrupting ck ck command write nop nop bank a, col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n t10 t11 nop twr trp *2 don?t care di n = data in for column n twr is referenced from the first positive ck edge after the last data in pair dm= dm0 ~ dm3 an interrupted burst of 4 or 8 is shown, 1 data element is written a8 is low with the write command (auto precharge is disabled) *1 = can be don't care fo r programmed burst length of 4 *2 = for programmed burst length of 4, dqs becomes don't care at this point *1 *1 *1 *1 pre bank (a or all)
etrontech em6a9320bib etron confidential 47 rev 1.0 july /2012 figure 27. precharge command ck ck cke cs ras cas we a0-a7, a9-a11 a8 don?t care high all banks one bank ba ba0,1 ba= bank address (if a8 is low, otherwise don't care)
etrontech em6a9320bib etron confidential 48 rev 1.0 july /2012 figure 28. power-down ck ck cke valid command don?t care t0 t1 t2 t3 t4 tn tn+1 tn+2 tn+3 tn+4 valid tn+5 tn+6 nop nop no column access in progress enter power-down mode exit power-down mode t is t is figure 29. clock frequency change in precharge ck ck cmd t is t0 t1 t2 t4 tx tx+1 ty ty+1 ty+2 ty+3 ty+4 tz nop nop nop dll reset nop valid nop frequency change occurs here stable new clock before power down exit t rp minmum 2 clocks required before changing frequency 200 clocks cke
etrontech em6a9320bib etron confidential 49 rev 1.0 july /2012 figure 30. data input (write) timing dqs dq don?t care t ds di n dm t dh t ds t dh t dqsh t dqsl di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n figure 31. data output (read) timing ck ck dq t ch t cl t qh t dqsq max t qh max t dqsq burst length = 4 in the case shown dqs
etrontech em6a9320bib etron confidential 50 rev 1.0 july /2012 figure 32. initialize and mode register sets t is t ih nop pre emrs mrs pre ar ar mrs act code code code ra tvdt>=0 t ch t cl t ck t is t ih t is t ih code code code ra t is t ih t is t ih all banks t is t ih all banks ba0=h ba1=l ba0=l ba1=l ba0=l ba1=l ba t is t ih high-z high-z lvcmos low level ck ck dm a0-a7, a9-a11 command vref cke a8 ba0,ba1 dqs dq vdd vddq vtt (system*) *=vtt is not applied directly to the device, however tvtd must be greater than or equal to zero to avoid device latch-up. ** = tmrd is required before any command can be applied, and 200 cycles of ck are required before any executable command can be applied the two auto refresh commands may be moved to follow the first mrs but precede the second precharge all command. don?t care power-up: vdd and clk stable extended mode register set load mode register, reset dll (with a8=h) 200 cycles of ck** load mode register, (with a8=l) t=200s **t mrd **t mrd t rfc t rfc **t mrd t rp
etrontech em6a9320bib etron confidential 51 rev 1.0 july /2012 figure 33. power down mode ck ck cke valid* command don?t care valid t ck nop nop enter power-down mode exit power-down mode t ch t cl t is t is t ih t is t is t ih valid t is t ih addr valid dqs dq dm no column accesses are allowed to be in progress at the time power-down is entered *=if this command is a precharge all (or if the device is already in the idle state) then the power-down mode shown is precharge power down. if this command is an active (or if at least one row is already active) then the power-down mode sh own is active power down.
etrontech em6a9320bib etron confidential 52 rev 1.0 july /2012 figure 34. auto refresh mode ck ck a0-a7 a9-a11 valid nop command t is don?t care t ih nop ar nop ar nop nop act t is t ih t ch t cl t ck ra cke ra a8 ba0,ba1 dqs dq *bank(s) valid nop pre ra all banks one banks ba t ih t is dm t rp t rfc t rfc * = don't care , if a8 is high at this point; a8 must be hi gh if more than one bank is active (i.e., must precharge all active banks) pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh nop commands are shown for ease of illustration ; other valid commands may be possible after trfc dm, dq and dqs signals are all don't care /high-z for operations shown
etrontech em6a9320bib etron confidential 53 rev 1.0 july /2012 figure 35. self refresh mode ck ck cke nop command don?t care valid t ck ar nop clock must be stable before exiting self refresh mode enter self refresh mode t ch t cl t is t is t ih t is t is t ih addr valid dqs dq dm t is t ih t rp* t xsnr/ t xsrd** exit self refresh mode * = device must be in the all banks idle state prior to entering self refresh mode ** = txsnr is required before any non-read command ca n be applied, and txsrd (200 cycles of ck) is required before a read command can be applied.
etrontech em6a9320bib etron confidential 54 rev 1.0 july /2012 figure 36. read without auto precharge ck ck address nop t is t ih pre nop nop valid valid valid t is t ih t ch t cl t ck cke dm dqs nop read ra t ih t is dq cl=3 t rp act nop nop nop col n t is t ih ra all banks one banks bank x t is t ih dis ap *bank x bank x t rpre t dqsck min t rpst t lz t lz t ac min dqs dq t rpre t rpst t lz t lz max t dqsck t hz max t ih max max min min don?t care do n = data out from column n pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = don't care , if a8 is high at this point nop commands are shown for ease of illustration; other commands may be valid at these times precharge may not be issued before tras ns after the active command for applicable banks do n do n command a8 ba0,ba1 max t ac case 1: t ac /t dqsck =min case 2: t ac /t dqsck =max
etrontech em6a9320bib etron confidential 55 rev 1.0 july /2012 figure 37. read with auto precharge nop t is t ih nop nop nop valid valid valid t is t ih t ch t cl t ck ra nop read ra t ih t is cl=3 t rp act nop nop nop col n t is t ih ra bank x t is t ih en ap bank x t rpre min t rpst t lz t ac min t rpre t rpst t lz t lz max t dqsck t hz max t ih min max max don?t care do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n en ap = enable autoprecharge act = active, ra = row address nop commands are shown for ease of illustration ; other commands may be valid at these times the read command may not be issued until trap has been satisfied. if fast autoprecharge is supported, trap = trcd, else the rea d may not be issued prior to trasmin (bl*tck/2) do n do n max t ac min t lz t dqsck ck ck a0-a7 command cke a8 ba0,ba1 dm dqs dq dqs dq a9-a11 case 2: t ac /t dqsck =max case 1: t ac /t dqsck =min
etrontech em6a9320bib etron confidential 56 rev 1.0 july /2012 figure 38. bank read access nop t is t ih nop nop read t is t ih t ch t cl t ck nop act ra t ih t is t rc nop pre nop nop ra t is t ih col n all banks one banks dis ap bank x t rpre min t rpst t lz t lz t ac act ra ra ra ra *bank x bank x t is t ih bank x t ras t rcd t rp t dqsck min min t rpre max t lz t ac max max t rpst t dqsck don?t care do n = data out from column n pre = precharge, act = active, ra = row address, ba = bank address burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = don't care , if a8 is high at this point nop commands are shown for ease of illustration ; other commands may be valid at these times note that trcd > trcd min so that the same timing a pplies if autoprecharge is enabled (in which case tras would be limiting) do n do n min cl=3 max t lz max t hz dq dqs case 2: t ac /t dqsck =max dq dqs case 1: t ac /t dqsck =min dm ba0,ba1 command cke ck ck a8 a9-a11 a0-a7
etrontech em6a9320bib etron confidential 57 rev 1.0 july /2012 figure 39. write without auto precharge ck ck a0-a7 a9-a11 nop command t is t ih nop nop nop valid t is t ih t ch t cl t ck ra cke a8 ba0,ba1 dqs nop write ra t ih t is dq t dsh pre nop nop act col n t is t ih ra all banks one banks bank x t is t ih dis ap *bank x ba t wpres case 1: t dqss =min di n t ih t dqss t dsh t dqsh t dqsl t wpst t wpre dm dqs dq t dss t wpres case 2: t dqss =max di n t dqss t dss dm t wr t rp t dqsh t wpst t dqsl t wpre don?t care di n = data in from column n pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh burst length = 4 in the case shown 3 subsequent elements of data in are prov ided in the programmed order following di n dis ap = disable autoprecharge *= don't care , if a8 is high at this point nop commands are shown for ease of illustration; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge precharge may not be issued before tras ns after the active command for applicable banks
etrontech em6a9320bib etron confidential 58 rev 1.0 july /2012 figure 40. write with auto precharge ck ck a0-a7 a9-a11 nop command t is t ih nop nop nop valid t is t ih t ch t cl t ck ra cke a8 ba0,ba1 dqs nop write ra t ih t is dq t dsh nop nop nop act col n t is t ih ra bank x dis ap ba t wpres case 1: t dqss =min di n t dqss t dsh t dqsh t dqsl t wpst t wpre dm dqs dq t dss t wpres case 2: t dqss =max di n t dqss t dss dm t dal t dqsh t wpst t dqsl valid valid t wpre don?t care di n = data in from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following di n en ap = enable autoprecharge act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge
etrontech em6a9320bib etron confidential 59 rev 1.0 july /2012 figure 41. bank write access ck ck a0-a7 a9-a11 nop command t is t ih nop write nop t is t ih t ch t cl t ck cke a8 ba0,ba1 dqs nop act all banks t ih t is dq t dsh nop nop nop pre ra t is t ih bank x dis ap *bank x t wpres case 1: t dqss =min di n t dqss t dsh t dqsh t dqsl t wpst dm dqs dq case 2: t dqss =max t dqss t dss dm t ras t dqsh t wpst col n ra ra one bank t is t ih bank x t wr t rcd t wpre t dss t dqsl t wpres di n don?t care di n = data in from column n pre = precharge, act = active, ra = row address, ba = bank address burst length = 4 in the case shown 3 subsequent elements of data out are provid ed in the programmed order following di n dis ap = disable autoprecharge *= don't care , if a8 is high at this point nop commands are shown for ease of illustration; other commands may be valid at these times although tdqss is drawn only for the first dqs rising ed ge, each rising edge of dqs must fall within the + 25% window of the correspondi ng positive clock edge precharge may not be issued before tras ns after the active command for applicable banks t wpre
etrontech em6a9320bib etron confidential 60 rev 1.0 july /2012 figure 42. write dm operation ck ck a0-a7 a9-a11 nop command t is t ih nop nop nop valid t is t ih t ch t cl t ck ra cke a8 ba0,ba1 dqs nop write ra t ih t is dq t dsh pre nop nop act col n t is t ih ra all banks one banks bank x t is t ih dis ap *bank x ba t wpres case 1: t dqss =min di n t dqss t dsh t dqsh t dqsl t wpst dm dqs dq t dss t wpres case 2: t dqss =max di n t dqss t dss dm t wr t rp t dqsh t dqsl t wpre t wpst don?t care di n = data in from column n pre = precharge, act = active, ra = row address, ba = bank address burst length = 4 in the case shown 3 subsequent elements of data in are provid ed in the programmed order following di n dis ap = disable autoprecharge *= don't care , if a8 is high at this point nop commands are shown for ease of illustration ; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge precharge may not be issued before tras ns after the active command for applicable banks t wpre
etrontech em6a9320bib etron confidential 61 rev 1.0 july /2012 figure 43. 144 ball lfbga package outline drawing information units: mm detail : "a" "a" pin #1 top view side view bottom view dimension in inch dimension in mm symbol min nom max min nom max a -- -- 0.055 -- -- 1.40 a1 0.012 0.014 0.016 0.30 0.35 0.40 a2 0.036 0.038 0.040 0.91 0.96 1.01 d 0.469 0.472 0.476 11.90 12.00 12.10 e 0.469 0.472 0.476 11.90 12.00 12.10 d1 -- 0.346 -- -- 8.80 -- e1 -- 0.346 -- -- 8.80 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50

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